Vias are routinely used in forming semiconductor ICs. Vias may be formed that extend vertically for the full die thickness from the bottomside of the die to one of the contact level or one of the metal interconnect levels, such as metal 1 on the active topside of the die. In the case of silicon substrates, such structures are often referred to as “through-silicon-vias”, and are referred to more generally herein as through-substrate-vias (TSVs). The TSV vertical electrical paths are significantly shortened relative to conventional wire bonding technology, generally leading to significantly faster device operation.
TSVs are generally framed by a dielectric liner (or dielectric sleeve) and are filled with an electrically conductive core comprising copper or another electrically conductive filler material to provide the desired low resistance vertical electrical connection. The dielectric liner is generally from about 0.2 μm to 5 μm thick. A diffusion barrier metal layer on the dielectric liner frames the TSV and protects against migration of the TSV filler material into the substrate. In the case of highly mobile metal TSV filler materials that are known to significantly reduce minority carrier lifetimes in the semiconductor, such as copper in the case of silicon, migration can cause problems such as significantly increased junction leakage or a shift in transistor threshold voltage. The diffusion barrier metal layer is typically 100-500 Å thick. In the case of an electroplated metal (e.g., copper) process, a seed layer is generally added after the diffusion barrier metal layer before electroplating the TSV filler metal.
The coefficient of thermal expansion (CTE) is defined as the fractional increase in the length per unit rise in temperature. Copper, as well as some other TSV filler materials, have a significantly higher CTE as compared to conventional semiconductor substrates, such as silicon, and as compared to conventional dielectric liners.
For example, around room temperature copper has a CTE of approximately 17 ppm/° C., whereas silicon has a CTE of approximately 2 to 3 ppm/° C., while silicon dioxide has a CTE of about 0.6 ppm/° C. Such CTE mismatches (ACTE) can result in significant thermally induced stress in the TSV as well as the silicon substrate including the circuitry (e.g. MOS transistors) in the silicon (or bother substrate material) surrounding the TSVs, particularly during certain fab processing subsequent to the fabrication of the TSV (e.g., 360° C. to 410° C. sinters), during assembly and test/operations as may occur during solder reflow (e.g., up to about 260° C.) or during thermo-compressive bonding (e.g., up to 400° C.), during certain temperature cycle reliability testing (e.g., −55° C. to 125° C.), or even during long-term field operation of the die. The CTE mismatch between the dielectric liner and TSV filler material can lead to diffusion barrier metal layer failures (e.g., ruptures or peeling) which allows metal (e.g., copper) migration into the substrate.
A number of solutions have been proposed to reduce problems caused by CTE mismatches for ICs having copper TSVs. In some IC designs, to reduce stress, TSVs are positioned in TSV arrays comprising a plurality of TSVs. For example, reducing the TSV diameter and increasing TSV spacing (i.e. TSV pitch) generally reduces stress. Another known option to reduce stress is to use a TSV filler material that provides a lower ACTE relative to the substrate (e.g., silicon), such as tungsten instead of copper.